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| Table 5.9 Virtual to real address translation. |
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(a) Translation (T) action with each memory reference. |
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(b) ''Not in TLB" cycles for a translation miss. Can be costly if TB is too small. |
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| | In order to avoid translate (T) delay, we can use: | |
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(a) Virtual cache. |
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(b) Set associativity (of sufficient depth). |
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(c) Colored bits page assignment. |
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Tc.miss = Taccess + (L - 1) Tbus cycle, |
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as described in the above case study. (Also, see the next chapter.) |
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This is a useful measure when there is no good model for CPU time. As before, the goal is to minimize the effective memory access time or provide the minimum effective memory access for a given cost. |
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For bus-based processors (especially multiprocessors), bus traffic can be an important limitation on performance. As bus saturation approaches, contention for the bus increases the waiting time for memory service and hence increases the Teff.mem. time significantly. When bus saturation occurs, it is necessary to consider the bus traffic caused by the memory system. Usually, this is not a simple process of reducing memory traffic, since a single-word transfer occupies significantly more bus time than a multiword transfer. The goal then in reducing bus traffic is primarily to reduce the number of separate bus requests, even if the number of words transferred increases. |
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5.16 Virtual-to-Real Translation |
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So far in this chapter, we have assumed that the cache is accessed with a real memory address: the address translated by the TLB (translation lookaside buffer) or similar mechanism into the address used by the physical memory. There are at least three important performance aspects that directly relate to virtual-to-real address translation: |
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1. Improperly organized or insufficiently sized TLBs may create excess not-in-TLB faults, adding time to program execution. |
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2. For a real cache, the TLB access time must occur before the cache access, effectively extending the cache access time. |
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3. Two-line addresses (for example, an I-line and a D-line address) may be independent of each other in the virtual address space yet collide |
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