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Setting the condition code |
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| | A BC instruction uses a mask to test for a particular condition or combination of conditions. The four-bit mask is ANDed with the four condition code states, PNZO; these result bits are then ORed to determine the outcome. If the result is ''1," the branch is taken (i.e., is successful); if the result is "0," the branch is not taken and sequencing contunues in line. | | | |
| Mask = 0000 | is no op, since all conditions are masked outproducing 0s from the ANDing operation | | Mask = 1111 | is unconditional branch, since the previous computation must have produced some result (P, N, Z, O ) and at least one mask AND condition will be true. | | Mask = 1010 | selects the condition P or Z, and branch is taken if result is > 0 (e.g., BC. GE). | | Mask = 0110 | Similarly, the condition selected is N or Z, and branch is taken if result is < 0 (e.g., BC. LE.). |
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Figure1.15
Examples of setting and using the condition code. |
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Many architectures include special support for loop control by branch-on-count-type instructions. In branch-on-count (BCT), the contents of a specified register are decremented by one and then tested. If the contents are nonzero, control transfers to the second operand address. The condition code is both untested and unaffected. This can be generalized where an arbitrary value can be used in place of the "one" used in the BCT. An index value contained in a register is added to a first operand register, and the result is compared to an unnamed implied register. If the new sum is less than or equal to the contents of the implied register, transfer of control takes place to the address specified by the third operand; otherwise, control passes to the next instruction in sequence. This add, compare, and branch sequence is in the VAX instruction repertoire. RISC processors forego these extended loop control instructions, since they can be synthesized from sequences of ALU and branch-on-condition instructions. |
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