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| Table 1.15 Addressing mode summary. |
| | Mode | Specification | Explanation | | Register | RX | Register X | | Memory | ADDR | Address specified by ADDR | | Indirect | [RX] | Address specified by the contents of RX | | Indexed | OFFSET[RX] | Address specified by OFFSET plus contents of RX | | Immediate | #val | The value val |
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1.5.5 Register Sets and Addressing Modes |
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Another area where there is virtually no hope of standardization is in referencing data. The simplest form of data addressing is accessing registers. While most processors use numbered registers, some processors (such as the Intel x86 series) use named registers,10 and others (such as the Motorola 680x0 series) use several different sets of numbered registers, each with a different specifier. |
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Some instructions use implied registers that are not named by the instruction, but are used nonetheless. The most common instructions of this sort are jump and branch instructionsthe PC register is inferred from the instruction. Older microprocessor architectures, such as the Intel x86 series, used many implicit register references. |
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As was mentioned earlier, even the order of register arguments for an instruction varies. Often, registers may be part of the general-purpose register set but have predefined meanings. The most common predefined register used in such a way is the stack pointer. More recently, processors have begun to define register 0 to have the value "0." This has several advantages. First, 0 is a commonly used value in both data (for example, in comparisons) and memory reference (as in a 0 index or offset) instructions. Additionally, having a 0 value removes the need for special operations (such as a move or a clear of the destination). Consider the following four operand instructions: |
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ADD.W R3, R0, #14h ;load the value 14 (hexadecimal) into R3
ADD.W R6, R0, R1 ;move R1 to R6
SUB.W R0, R11, R8 ;compare R11 and R8 (condition code
;to be tested later)
AND.B R0, R5, #02h ;test for bit 1 set (condition code
;to be tested later) |
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Each of the preceding instructions can functionally replace a completely unrelated instruction (e.g., CMP.W with SUB.W), thus reducing the number of instructions required and therefore the complexity of the machine. |
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Table 1.15 summarizes the modes that this text uses. Note that when specific values are not necessary, italicized prototypes (Rd for destination, Rs1 |
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10The Intel x86 actually has different names for registers to distinguish between different data typesthus, EAX is a 32-bit register, AX is the low 16 bits of the EAX register, and AH and AL are the high and low bytes of the AX register. |
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