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Figure 5.38
L2 miss rates with a 32KB L1 cache (data from Przybylski [237]). |
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3. The level-two cache, so long as it is significantly larger than the levelone cache, is completely independent of the level-one cache's parameters; its miss rate corresponds to a solo miss rate. Thus, the memory hierarchy problem can be decomposed into the design of individual levels. |
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| Miss in L1, hit in L2: | 2 cycles | | Miss in L1, miss in L2: | 7 cycles |
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Suppose we have a two-level cache with miss rates of 4% (L1) and 1% (L2). Suppose the miss in L1 and hit in L2 penalty is 2 cycles, and the miss penalty in both caches is 7 cycles (5 cycles more than a hit in L2). If a processor makes 1.5 references per instruction, we can compute the excess CPI due to cache misses as follows: |
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