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Excess CPI due to L1 misses |
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1.5 refr/inst ´ 0.04 misses/refr ´ 2 cycles/miss |
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Excess CPI due to L2 misses |
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1.5 refr/inst ´ 0.01 misses/refr ´ 5 cycles/miss |
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Note: the L2 miss penalty is 5 cycles, not 7 cycles, since the 1% L2 misses have already been "charged" 2 cycles in the excess L1 CPI. |
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excess L1 CPI + excess L2 CPI |
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True or logical inclusion, where all the contents of L1 reside also in L2, should not be confused with statistical inclusion, where usually L2 contains the L1 data. There are a number of requirements for logical inclusion. Clearly, the L1 cache must be write-through. (The L2 need not be.) If L1 were copyback, then a write to a line in L1 would not go immediately to L2, so L1 and L2 would differ in contents. The following example shows that inclusion fails in many cases. |
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Consider a 2-line direct mapped L1 cache with a 4-line fully associative L2 cache (both with the same line sizes): |
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Designate a reference to line E1 in L1 as an R1 reference, and a reference to line E2 as an R2 reference, then associate a sequence number R1 - 1 as the first line to go into E1 and R1 - n as the nth line. Consider the sequence: |
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R2 - 1, R1 - 1, R1 - 2, R1 - 3; |
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i.e., a reference to E2, then three references to (new) lines in E1. The cache contents would be: |
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