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Figure 5.37
L2 miss rates with a 4KB LI cache (data from Przybylski [237]). |
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2. The global miss rate of a cache is the number of L2 misses divided by the number of references made by the processor. This is our primary measure of the L2 cache. |
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3. The solo miss rate is the miss rate the cache would have if it were the only cache in the system. It is the miss rate defined by the principle of inclusion. If L2 contains all of L1 then we can find the number of L2 misses from our DTMR and the processor reference rate, ignoring the presence of the L1 cache. The principle of inclusion specifies that the global miss rate will be essentially the same as the solo miss rate, allowing us to use the solo miss rate to evaluate our design. |
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The principle of inclusion for a pair of two-level caches can be assessed in Figures 5.37 and 5.38. Figure 5.37 shows the miss rates for a L2 cache with a 4KB level-one cache, while Figure 5.38 shows the L2 miss rate with a 32KB level-one cache. |
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If the second-level cache is truly inclusive of the first-level cache, the global and solo cache miss ratios would be coincident in Figure 5.38 so long as L2 was equal to or greater than the L1 cache size. A discrepancy illustrated in these figures arises because the L2 cache did not have the same degree of set associativity as the L1 cache. It was ''inclusive" only on a statistical basis, not on a complete logical basis. |
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The preceding data (read misses only) illustrate some salient points in multilevel cache analysis and design: |
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1. The local miss rate of a second-level cache is quite dependent upon the behavior of the level-one cache. |
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2. So long as the level-two cache is the same as or larger than the level-one cache, analysis by the principle of inclusion provides an excellent estimate of the behavior of the level-two cache. |
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