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Figure 5.34
Miss rate relative to an unsectored cache with line and transfer
width (physical word size) of 4 bytes. Line overhead is the
number of bits associated with each line entry in the cache
directory (except for case of fully associative cache with CAM:
see text). |
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processor is brought into the data array. A valid/invalid bit (not shown in Figure 5.33) indicates the status of the sub-lines. If a subsequent access is made to another sub-line in this newly loaded line, that sub-line is then brought into the cache. The effect of the sectored cache is to diminish somewhat the value of spatial locality, but to retain the temporal locality of the cache, and to greatly diminish the size of the directory. |
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The overall effect of this can be seen in Figures 5.34 and 5.35. Both of these figures show the miss rate of sectored caches relative to an unsectored cache for various line sizes and transfer widths of four bytes (Figure 5.34) and eight bytes (Figure 5.35). For the commonly used transfer width of four bytes, if the directory entry overhead exceeds 32 bits per line (line overhead), then the sectored caches provide better overall performance for most configurations except for the line size of 64. Notice that Figures 5.34 and 5.35 do not include the effect of the miss penalty itself. They describe the miss ratio only. Measuring actual miss rates and including the effects of the actual miss penalty itself further favors sectored caches. |
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Frequently the designer encounters a situation where, for one reason or another, the first-level cache has been specified and designed (as in the case of an on-chip first-level cache) and a larger second-level cache must be added to the system to improve overall performance. This situation occurs frequently in multiprocessor configurations whose special considerations |
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