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| Table 5.6 Quantity of data storage (bytes) available in a cache with various line overhead values and a total available area of 1,024 byte- or 8,192 bit-area equivalents (from Mulder [207]). | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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One can estimate the number of overhead bits directly from the structure of the cache directory with one exception. If a fully associative cache memory is used, using a content address memory (CAM), the CAM bit occupies approximately twice the area of a data bit. This factor of two can then be used in determining the overhead. Table 5.6 shows the effect of line size on area utilization for various directory overheads. The table assumes that there is a table bit area equivalent for the cache of 8,192 data bits (1,024 data bytes) if there were no directory overhead. The table shows that the amount of space in the cache available for data storage varies dramatically with a line overhead, especially for line sizes less than 16. It varies less for larger line sizes. From this, we can see the usefulness of large blocks to the on-chip cache designer. Unfortunately, the use of large lines, especially for small caches, causes an increase in the miss rate and especially increases the total miss time. This makes some sort of a compromise a necessity. One compromise is a sectored cache. |
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In a sectored cache (Figure 5.33), each line is broken into transfer units (a type of sub-line that represents one access from the cache to the memory). The directory is organized around the line size insofar as the address tags, etc., are concerned. When a miss occurs in a cache, the missed line is entered into the directory, but only the transfer unit that is required by the |
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Figure 5.33
Sectored cache. A bit in each sub-line indicates validity of that
sub-line. |
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