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0303-01.gif
Figure 5.35
Miss rate relative to an unsectored cache with line and transfer
width (physical word size) of 8 bytes. Line overhead is the
number of bits associated with each line entry in the cache
directory.
Microprocessor Caches
For reasons outlined in this chapter, modern microprocessor systems are moving in the following directions:
1. Split I- and D-caches. This ensures (especially for L/S processors) adequate cache-processor bandwidth. Some processors have implemented an I-cache only. This is probably not a good idea, since data access time to memory tends to dominate execution time. Except in extraordinary cases, some cache area should be allocated for both I and D functions.
2. The use of sectored caches. To optimize the area available for storing data, the sectored cache minimizes the directory size and affords an overall best marginal use of area.
3. Two-level cache, where the on-chip cache is supported by a larger, off-chip or even on-chip second-level cache. The two-level cache improves performance by effectively lowering the first-level cache access time and miss penalty.

 
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