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In order to optimize the design of an on-chip cache, consider the area model introduced in chapter 2 based on the register bit equivalent (the rbe). Since presumably both the cache directory and the cache array are made from the same technology, we are not concerned (as we were in chapter 2) with normalizing the per-bit area costs over the two different technologies: registers and caches. Here, we assume that the cost of a directory bit n is the same as the cost of a data bit: |
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area for cache directory bit |
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The area used by the directory represents overhead to the overall cache design, since the directory holds no cache data. Associated with each line in the cache or data array is an entry in the directory. Suppose we designate the amount of area occupied by a directory entry as the bit area units. In Table 5.6, we assume that the total area available for a cache in the directory is 1,024 byte area units, or 8,192 bit area units. This area must accommodate both the directory and the data array. Table 5.6 shows the amount of area available for the data array after the bits of directory overhead per line have been allocated to the directory. Thus, if there were no line overhead, i.e., n = 0, we would have 1,024 byte area equivalents available for the data array independent of block size. Of course, n = 0 is an unrealizable cache configuration, since it eliminates the directory completely. A simple direct-mapped cache may have a rather small overhead per line, sufficient only to contain the tag portion of the address. Suppose such an overhead was 32 bits. For very small line sizessay, 16 bits or 2 bytesthe directory still occupies approximately twice as much area as the data array, since each line has 32 bits of directory area and only 16 bits of data area and, as shown in Table 5.6, only 341 data bytes are available for storing data. Increasing line size decreases the number of entries in the directory and decreases the line or directory overhead, so that using a 64-byte line and the same 32-bit (n = 32 bit) overhead allows the data array to have effectively 964 bytes out of the total 1,024 bytes available. |
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The directory overhead (or the line overhead) is inversely proportional to the line size and the number of bits contained in the entry. A typical entry includes an address tag, valid bits, and replacement information. If the number of data bytes per line is represented by b, then the cache utilization factor is: |
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Cache utilization is a rough estimate of the fraction of area available for data storage compared to the total area. Thus, a line size of 2 bytes with a block line overhead of 32 bits has a cache utilization of 2÷(2+32÷8) = 1/3, hence 1,024 ´ .33 = 341. Larger line sizes make more of the area available for the data array and require less to hold the directory. |
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A single line of b bytes has an area of 8b area units and has an overhead of: |
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Overhead = n bit area equivalents. |
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