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Split Instructions and Data (I/D Split) |
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Twice the access bandwidth available to the CPU, i.e., simultaneous instruction and data access. |
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Poorer hit rate than same amount of integrated cache. |
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More hardware for control. |
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Figure 5.32
On-chip cache: how to organize the cache so as
to maximize the data area (and minimize the
directory). |
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On-chip caches behave like any other type of cache with two notable exceptional considerations: |
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1. Because of pin limitations, the transfer path to and from memory is usually limited, frequently to four bytes and generally to a maximum of eight bytes. |
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2. The cache organization must be optimized to make the best use of the allocated area. |
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This latter consideration drives the designer to keep the cost of the directory small so that the bulk of the area available for the cache is available for the data array. This favors caches that require fewer directory entries, caches that are simply organized (e.g., direct mapped), and caches with large block sizes. On the other hand, these cache limitations may increase the cache miss rate, and large block sizes certainly increase the time that the processor is idle handling the cache miss. A relatively narrow transfer path also restricts the designer's flexibility in arranging or managing large blocks. |
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