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Figure 5.31
Instruction traffic (relative to R/M) for a compiler application, from
Mitchell [200]. "Ideal" represents the cache size that contains the whole
program. |
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size and spikes are measured in terms of relative performance only. For certain cache sizes, the more dense architecture captures most of its program localities and as a result has a very low miss rate. |
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Aside from the instruction set, compilers, and register allocators in particular, can have a significant effect on cache performance by affecting code density. Some compiler optimizations improve code density (and hence cache performance), and some reduce it. Optimizations that eliminate redundant instructions improve code density. Optimizations such as loop unrolling that are targeted at reducing branch frequency have the side effect of reducing code density. Because of the variance in compiler optimizations, there is no easy way to adjust our cache data for instruction set differences. The data presented is for the R/M architecture with optimized compilation. Presumably, a well-designed L/S instruction set architecture with advanced register allocation (taking advantage of the 32 registers) would achieve a relative code density significantly better than the factor of 1.39 mentioned earlier. |
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In predicting an L/S miss rate from (adjusted) DTMR data, the user should consider the robustness of the instruction set and the kind of compiler optimizations that are anticipated. Overall, it is likely that L/S I-cache performance will be worse than DTMR, probably by 20% to 40%. Integrated caches for L/S machines show fewer differences, probably no more than a 10% to 20% miss rate increase. |
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Since register allocation is an improving art, in the longer term the 32 registers in the L/S architecture should largely cancel the R/M architecture (with 16 registers) instruction size advantage. In the analyses in this book, we will not adjust L/S architecture over the R/M-based DTMR data. In particular cases, the designer may wish to make adjustments as suggested above. |
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