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Figure 5.12
Effect of different machine traces. |
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code and also has the poorest locality. As such only (S/370MVS) actually exceeds the miss rate projections of the design target miss rate. Overall, however, the DTMR represents a reasonable assessment of expected performance for modern processors. |
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The processor architecture and its organization play important roles in determining overall cache effectiveness. Better-encoded instruction sets have smaller-sized working sets, and hence they require smaller instruction caches to capture that working set and minimize the miss rate. The instruction working set is most affected by differences in architecture. |
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The data working set, on the other hand, is not directly affected by instruction set encoding, but is affected more by register set organization and register allocation policy. |
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Most of the data presented in this chapter is with respect to a reference architecture (Figure 5.9). This reference architecture is our R/M architecture, with 16 registers using a global register allocation. It is the architecture characterized by the chapter 3 design target R/M data. Architectures that do not correspond to the reference architecture (L/S or R+M) require an adjustment of the design target data. |
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The DTMR data is based on traces of individual programs running through to completion. These relatively large programs present the cache with the opportunity to capture the working set of the program and minimize the miss rate. If the same program were run in an environment that was interrupted (a multiprogrammed environment, or an environment that required a good deal of system services such as I/O), the miss rate would be higher. In an effort to distinguish environments, Smith [259] introduces a Q factor, where: |
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Q = average number of instructions executed between task switches. |
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The DTMR data then represent Q exceeding 100,000; the user program is run to completion. We discuss the effect of lower Q's and the presence of the system in later sections. |
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