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| Table 5.1 DTMR adjustments (detailed tables are found in Appendix A). | | Effect | DTMR assumes | Adjust for | Section | | Associativity | Fully assoc. | Direct mapped, set assoc. | 5.5 | | Line replacement | LRU | FIFO/random | 5.7 | | Writes | Copyback | Write through (exclude write reference traffic) | 5.6 | | Systems | One user, no systems effect | System, multiprogramming transactions | 5.8 | | Instruction set | R/M | L/S | 5.10 | | Type | Integrated | I-cache, D-cache, other | 5.95.12 |
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Figure 5.13
Miss rate for different set associativities (16-byte
lines). |
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5.5 Adjusting the Data for Cache Organization |
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The DTMR data assumes a fully associative cache with LRU replacement. For caches of other design, adjustments must be made to the DTMR data (Table 5.1). Figure 5.13 shows the effect on miss rate of varying degrees of set associativity (16-byte lines). The lower the associativity (i.e., the closer to direct mapped), the poorer the miss rate. This can be expressed as a correction factor for the DTMR. Thus, in Figure 5.14, the relative miss rate data for various cache line sizes and combinations is expressed relative to the corresponding DTMR caches. For a 16-byte line, direct mapped 32-kbyte cache, we would multiply our DTMR miss rate from Figure 5.10 by a factor of 1.45 (given by Figure 5.14). |
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