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5. Following study 4.4 and the assumptions of problem 1, compare delayed branch and early condition code setting for each of the timing templates. (Note: TIF takes the same number of cycles as a DF.) |
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(a) IBM 3033. |
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(b) Amdahl V-8. |
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(c) MIPS R2000. |
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Treat "half-cycles" as full cycles. |
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6. For the statement C := A + B and the assumptions of study 4.9, find the code and timing for our R/M machine with the IBM 3033 timing template. Again use the assumptions of problem 1. |
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7. Describe I-buffer arrangements (number of in-line and target registers) suitable to each of the IBM 3033, Amdahl V-8, and MIPS R2000 timing templates and for w (the size of the IF path) = 4 and 8 bytes. Assume branch prediction is used. |
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8. A certain store buffer has a size of 4 entries. The mean number used is 2 entries. |
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(a) Without knowing the variance, what is the probability of a "buffer full or overflow" delay? |
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(b) Now suppose the variance is known to be s2 = 0.5; what is the probability of such a delay? |
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9. Determine an effective static branch prediction strategy for the following timing templates: |
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(a) The Amdahl V-8. |
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(b) The MIPS R2000. |
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Treat "half-cycles" as full cycles. Follow study 4.6, then use data in study 4.7. |
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10. Modify the interlock of study 4.9 for an L/S architecture and MIPS R2000-type timing template. |
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11. Suppose the processor timing in study 4.10 was based on a machine with split I- and D-cache (cache miss of 6 cycles). Assume that all the code is initially present as a block in the I-cache, but that a store into a block in the I-cache invalidates that entry. Show the effect on the timing. |
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12. (a) Suppose a certain processor has the following BC behavior: A three-cycle penalty on correct guess of target, and a six-cycle penalty when it incorrectly guesses target and the code actually goes in-line. Similarly, it has a zero-cycle penalty on correct in-line guess, but a six-cycle penalty when it incorrectly guesses in-line and the target path is taken. The target path should be guessed when the probability of going to the target is known to exceed what percent? |
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(b) For an L/S machine that has a 3-cycle cache access and an 8-byte physical word, how many words (each 8 bytes) are required for the in-line (primary) path of an I-buffer to avoid runout? |
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