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H. S. Stone. High-Performance Computer Architecture, 2nd edition. Electrical and Computer Engineering. Addison-Wesley, Reading, MA, 1990. |
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J. A. DeRosa and H. M. Levy. An evaluation of branch architectures. Proceedings of the 14th Annual Symposium on Computer Architecture, pages 1016, June 1987. |
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J. E. Smith. A study of branch prediction strategies. Proceedings of the 8th Annual Symposium on Computer Architecture, pages 135148, May 1981. |
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1. Evaluate the performance (cycles per instruction) of processors based on each of the three templates (IBM 3033, Amdahl V-8, and MIPS R2000, assuming the same ALU operations) described earlier in the chapter. Assume all have the same (unit) cycle time, with the relative decode rate as shown in Section 4.2.1. Treat the ''half-cycles" as full cycles. Also assume that the CC is set at the end of the last EX cycle. Follow the assumptions of study 4.3. |
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2. Repeat study 4.2 for the R/M machine used in that study, but with the following code sequence: |
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LD R3, 1000[R1,R2]
ADD R3, 1008[R1,R2]
MPY R4, 2000[R1,R3]
ST 3000[R1,R3], R4
BC.NE* TARGET[R1,R3] |
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*Assume the ADD is the only instruction in this sequence that sets the CC. |
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Follow all other assumptions made in study 4.2. |
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3. Now repeat study 4.3, ignoring "run-on" effects, using design target data (scientific environment) from Chapter 3 for branch and address dependencies for the timing templates for: |
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(a) The IBM 3033. |
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(b) The Amdahl V-8. |
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(c) The MIPS R2000. |
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Treat "half-cycles" as full cycles. |
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4. Repeat study 4.3 using design target data (scientific environment) from Chapter 3. Assume that the only run-on instructions are the variable field length instructions (plus LDM and STM). The R/M architecture described includes these MM instructions. Calculate run-on effects as one EX cycle for each byte in the larger of the source operands. Note that the MM instructions necessarily have an extended timing template (for multiple AG, DF, etc.) and this must be included. |
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