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Figure 4.26
Decoder for a pipelined processor. |
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4.6.1 Decoder and Interlocks |
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In a well-mapped machine, the decoder is simply the sum of the microprogrammed routines and support hardware (or logic equations) that realize each of the operations in the machine vocabulary (See chapter 1.) In pipelined machines, several instructions are in execution during each cycle. In these machines, when an instruction is decoded, it is insufficient for the decoder to provide only control point and sequencing information. Proper execution depends on the other instructions in the pipeline. Thus, the decoder (Figure 4.26) must additionally determine: |
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1. Scheduling of the current instruction. The current instruction may be delayed if a data dependency (AG) is recognized or if an exception arisese.g., not in TLB notification, cache miss, etc., from a preceding instruction. |
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2. Scheduling of subsequent instructions. Later instructions may be delayed if, for example, the current instruction is in the "run-on" class so as to preserve order of execution. |
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3. Strategic path selection on branch instruction. |
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In mainframes, in order to speed instruction execution, only the execution unit is microprogrammedthe rest of the processor has fixed control. Thus, a single microinstruction can contain necessary controls and state information. |
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The data interlocks (sub-unit D in Figure 4.12) may also be part of the decoder. This sub-unit determines register dependencies and schedules the entry of the decoded instruction into the AG and EX units so as to ensure proper action. (See study 4.9.) The interlocks must ensure that the current instruction does not use (depend on) a result of a previous instruction until that result is available. |
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The "run-on" controller performs a similar function on subsequent instructionsensuring that they do not enter the pipeline until the execution unit is scheduled to complete the current "run-on" instruction, thus preserving the execution order. |
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