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Figure 4.24
Typical BTB structure. If "hit" in BTB, then
BTB returns target instruction to
processor; CPU guesses target. If "miss"
in BTB, then cache returns branch and
in-line path; CPU guesses in-line. |
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Consider the following timing sequence: |
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The BTB provides both the target instruction and the new PC (usually the latter is unnecessary when a branch adder is available). There is now no delay on a taken branch so long as the branch prediction is correct. Note that the branch itself must still be fetched from the I-cache and be fully executed. If either the AG outcome or the CC outcome is not as expected, all instructions in the target fetch path must be aborted. Clearly, no conditionally executed (target path) instruction can do a PA, as this would make it impossible to recover on a misprediction. |
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Figure 4.25
BTB outcome tree. |
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