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Page 237 Table 4.13 Fraction of branch targets found to have changed from previous execution of that branch. Workload Probability of Target Change Compiler 4.2% Business 2.1% Scientific 4.4% Supervisor state 1.4% Table 4.14 Branch target address buffer hit ratio (organized as a LRU stack). n Mix Definition Entries Compiler Business Scientific Supervisor State 1 0.031 0.121 0.158 0.012 2 0.075 0.150 0.223 0.066 4 0.185 0.212 0.272 0.154 8 0.298 0.247 0.402 0.259 16 0.369 0.315 0.636 0.275 32 0.514 0.412 0.693 0.301 64 0.634 0.624 0.812 0.435 128 0.769 0.832 0.953 0.545 256 0.888 0.929 0.970 0.615 512 0.967 0.968 0.993 0.672 and, if necessary, the pipeline can be flushed if the actual target differs from the stored target (an infrequent event; see Table 4.13). The effectiveness of such a branch target buffer depends on itshit ratio the probability that a branch is found in the BTB at the time it is fetched. Table 4.14 shows the hit ratios for various sizes of branch target buffers, where an entry is created whenever a branch is recognized and a global LRU replacement algorithm is used to remove the least recently used (executed) branch in the BTB in order to place a new entry into the BTB. The BTBs described previously that contain the target instruction(s) [129] are sometimes called target instruction buffers (TIB). TIBs have been used in implementations such as the AMD 29000. BTBs (or TIBs) can be used quite well in conjunction with the I-cache. Suppose we have a configuration as shown in Figure 4.24. The IF is made to both BTB and I-cache. If the IF ''hits" in the BTB, the target instruction that was previously stored in the BTB is now fetched and forwarded to the processor at its regularly scheduled time. The processor will begin the execution of the target instruction.
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