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Figure 4.13
Cache access controller. |
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A. Cache access controller. |
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B. I-buffer (including the I-register). |
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C. Instruction decoder (including branch and run-on instruction manager). |
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D. Data interlocks (including address interlock manager). |
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E. Store interlocks and store buffers. |
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Sub-units B, C, and D are closely related, with relatively more information flow among these units than external to them. Similarly, sub-units A and E control access to the storage system and are closely related to one another. Still, the decoder, for example, must be aware of actions taken by the cache access controller. |
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We look at each of these sub-units and their effect on system performance. |
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4.4.1 Cache Access Controller |
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Requests to the cache may come from one of five sources (Figure 4.13): |
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2. Data write (from AG and store buffer). |
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3. I-buffer: target I-fetch. |
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4. I-buffer: in-line I-fetch. |
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5. External access (I/O, etc.). |
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If, as usual, the rate of external accesses is low, these can be given highest priority to avoid problems such as I/O run-out or overrun (I/O buffer overflow). |
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Ignoring external accesses, cache access priority is usually arranged (highest to lowest): |
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