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Figure 4.12
Processor control unit. |
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Now the AG is delayed only one cycle, assuming the ALU result is "bypassed" to the AG stage (discussed later). |
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For most processor arrangements, there is not a significant performance difference between static and dynamic pipelines, as long as both must meet the in-order execution requirement. The primary difference is the use of additional dummy cycles in the pipeline. |
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We assume dynamic pipelines for most of this chapter and text. They are basic to out-of-order implementations, and simpler, static pipeline applications can be developed directly from techniques studied in the context of dynamic pipelines. |
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4.4 Design of a Pipelined Processor |
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With multiple instructions in various stages of execution, there are many design considerations and tradeoffs in pipelined processors. After the functional partitioning of the processor is complete, the timing template is determined, and initial performance estimates are made, the design of the control unit (or I-unit) can be begun and performance estimates refined. |
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Figure 4.12 shows the processor control unit and some basic interactions with the rest of the system. For our purposes, there are five separate sub-units in the control unit: |
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