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cache per cycle, we would soon create a resource conflict at the cache, since each instruction requires both an IF and a DF. As we shall see later and in Chapter 5, not every instruction need require its own IF. It may be possible to fetch multiple instructions at a time, or to otherwise reduce conflicting use of a scarce resource. In the remainder of this study, we ignore apparent resource contention at the cache. |
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to case 1, the instruction interpretation latency is ten cycles; that is, the total time from the initiation of the instruction fetch (IF) to the execution of indicated operation (setting of the condition code) without dependencies is ten cycles. Under ideal conditions, on each cycle boundary an instruction is fetched, an instruction is decoded, an address is generated, an operand (data) is fetched, and an execution is begun. Two accesses are made to memory in each cycle (one for instruction and one for data), one decode is performed per cycle, and an address generation is performed while two operations are being executed in the two cycles allowed for execution. The pipelined processor designed to support this arrangement has been partitioned into autonomous functional units and each unit is coordinated on cycle boundaries to accommodate this maximum rate; the decoder is an independent unit that can decode one operation each cycle, the same being true for the address generation unit. The memory must be designed to accommodate two accesses per cycle if we are to sustain this maximum rate. |
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Note the influence the architecture has on these requirements. A simple single-accumulator machine requires two fetches (one for instruction, one for data) each cycle (maximum rate). In a L/S architecture, we might expect to see, on average, fewer than one data reference per cycle, since there are none for the register-to-register instructions. While the architecture influences the distribution of functional operations, total performance depends more on the behavior of the instruction set, i.e., the distribution of various types of dependencies that arise during program execution. |
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(a) Unconditional Branch (BR) at *: |
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