|
|
 |
|
|
|
|
Only one instruction can occupy a single resource (D, AG, and cache access) at a time. As described in the following, segmented resources (EX, cache) allow only one instruction in any one segment at a time. |
|
|
|
|
|
|
|
|
In the following study, we evaluate the dependency effects in a simple pipelined processor with a typical R/M mainframe timing template. |
|
|
|
|
|
|
|
|
Study 4.1 Evaluating Dependency Effects |
|
|
|
|
|
|
|
|
In this study, assume an R/M architecture with a pipelined layout vaguely similar to the Amdahl V/8 mentioned earlier, but without alternate cycle decode and with a more simplified timing template. We assume that the memory access is a three-cycle pipelined (segmented) access to a cache memory, and that execution similarly has a two-cycle pipelined execution through the ALU. Pipelined or segmented access or execution means that the process is segmented into several stages so that three accesses to the cache can be going on simultaneously; but they are segmented so that they are in different phases of access. Thus, a three-cycle access to a cache might represent the following pipelined actions: |
|
|
|
|
|
|
|
|
1. Access to a cache directory. |
|
|
|
|
|
|
|
|
2. Access to a data array. |
|
|
|
|
|
|
|
|
3. Transmission of result to processor ALU. |
|
|
|
|
|
|
|
|
Each of these actions is segmented by registers that can independently hold intermediate results. Most processors that we see throughout the remainder of the text have segmented or pipelined accessing and/or execution units. It is important to realize that a three-cycle cache access does not mean that only one access can be made every three cycles. Rather, it means that one access can be made per cycle but a total of three cycles is required for any individual access to complete. |
|
|
|
|
|
|
|
|
We now assume that the following time is required to execute the actions comprising the instruction execution: |
|
|
|
|
| 3 cycles | | 2 cycles (average OP) | | 1 cycle | | 0 cycles Iincluded in EX) |
|
|
|
|
|
|
Now for the ideal case, we create the timing template or the sequence of actions that must occur for the execution of an individual instruction, and then show two instructions (located at * - 1 and *). This instruction sequence represents the maximum execution ratelimited by the resources (the decoder, the AG, etc.) of the system. The astute reader will notice that if in fact we had only the ideal case and we could make only one access to a |
|
|
|
|
|