5. The weighted occurrence of this delay is added to the minimum execution time found in (3).
6. Continue until the major delay classes have been assessed.
Dependencies or breaks generally arise from one of three causes:
1. Procedural dependencies or branches. The pipeline is delayed because in-line fetching of instructions is disrupted. The branch target must first be fetched before the pipeline can resume execution.
2. Data conflictsunavailability of a source operand. This can occur for several reasons; typically, the current instruction requires an operand that is the result of a preceding uncompleted instruction.
3. Resource contention or run-on effectsmultiple successive instructions using the same resource or an instruction with a long execution time that delays a successor instruction to preserve in-order execution.
We now summarize these for a simple pipelined processor.
Simple Pipelined Processor Break Evaluation Rules
1. Branch
(a) BC (in-line) instruction.
For the next instruction (* + 1), the decode (D) waits until the cycle following the CC set.
(b) BC (target).
Decode of target instruction waits until target is fetched (TIF) and CC is set.
(c) BR.
Decode of target waits for TIF of the BR.
2. Data
(a) Address dependency.
The AG stage of the pipeline of the dependent instruction waits for the execution of a prior instruction.
(b) Execution (PA).
The EX stage of the dependent instruction waits for completion (PA) of a prior instruction.
3. Run-on
On a run-on, the instruction following the run-on waits before entering execution (EX) for a time sufficient to ensure that its PA (final EX) occurs after the PA (or final EX) of the run-on instruction.
