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Figure 4.4
The Amdahl 470 V/8 processor (cycle time = 26 ns). |
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The 3033 processor was IBM's top-of-the-line flagship pipeline processor of the early 1980s. Compared with a contemporary machine, the Amdahl 470 V/8, the 3033 used a longer cycle time (57 ns) and fewer stages. While the 3033 uses a putaway cycle, results from the execution unit, if required by the address generation unit, can bypass the putaway cycle and forward results directly to the address generator. As with most large mainframe processors, the 3033 uses a dynamic pipeline with-in-order execution. The Amdahl 470 V/8 processor represents an alternate machine design to the 3033, although it executes exactly the same instruction set. In order to understand the timing on the V8 the reader should recall the Chapter 2 discussion of two-phased clocking systems. In Figure 4.4, clocks are designated as odd or even. Actions indicated for a particular phase must occur on that phase. Similarly, the address generation step has been decomposed into two steps, the register access (R) and the address generation (AG). The execution step now requires two cycles, EX1 and EX2, and the putaway step takes two cycles, error check (C) and write (W). A new instruction can be initiated (i.e., decoded) only every other cycle. Within the limitations of the two-phased clock, the result of one instruction can be forwarded, bypassing the putaway cycle, to an address generation unit. |
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Some Microprocessors: the MIPS R2000 |
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The R2000 is a statically pipelined L/S machine with a template bearing some similarity to the Amdahl 470 V/8. Since the R2000 uses a two-phase clock (as in other microprocessors), a separate action can be performed in each phase. As with the Amdahl 470, the granularity of an action is the phase time (or one-half the ''clock"). For purposes of our evaluation, we consider this phase time the same as the logical clock, which is the unit for our timing template. |
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Here, for an ALU instruction, we have: |
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For an LD instruction, we have: |
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The PA for the functional instructions is delayed to occur at the same relative sequence time as for the LD. Instructions are offset by two phase times |
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