the understanding that Type 1-Extended pipelines will behave in (almost) exactly the same manner.
Type 2: Dynamic pipelined machines that can be configured to allow out-of-order execution, yet retain in-order instruction decode. (Decode is also sometimes called instruction issue.) For this type of pipelined processor, the execution and putaway of all instructions (including LD/ST) is a function only of dependencies on prior instructions. If a particular instruction is independent of all preceding instructions, its execution can be completed independently of the successful completion of prior instructions.
Type 3: The third type of dynamic pipeline allows instructions to be issued out of order as well as completed out of order. A group of instructions is analyzed together, and the first instruction that is found to be independent of prior (uncompleted) instructions is decoded.
For our purposes, we assume a simple dynamic pipelined processor (Type 1) for this chapter. In Chapter 7, we look at more sophisticated dynamic pipelined processors of the second and third types.
4.2.1 Examples of Pipeline Implementations
The examples in this section illustrate some of the different ways in which the conceptual steps in the processing of an instruction can be mapped into a pipelined hardware structure. These examples assume no dependencies or delays among instructions.
Figure 4.3
The IBM 3033 processor (cycle time = 57ns).
Older Mainframes: the IBM 3033 and Amdahl 470 V/8 Processors (both R/M machines)
In the IBM 3033 processor, instructions and data are normally fetched from a cache memory that has a pipelined access time of two cycles. Consequently, the instruction fetch (IF) and operand fetch (DF) steps are each two cycles long.
The 3033 overlaps the instruction decode step (D) with the operand address generation step (AG). Both are performed in a single cycle called a decode/address cycle (DA). Figure 4.3 illustrates the timing of the 3033 pipeline.
Note the IA (instruction address generation) stage in this and other (Amdahl and MIPS) machines. This represents the incrementing of the instruction counter and subsequent address translation. In evaluating performance we usually ignore this stage, as its outcome can normally be anticipated.
