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| Table 4.5 Types of pipelined processors. |
| | Type | | Max # of Instr Decoded per Cycle |
| Comment | | Static pipeline | | All actions in order | | Dynamic pipeline Type 1 * | | All D and all PA in order | | Dynamic pipeline Type 2 | | All D in order PA unordered | | Dynamic pipeline Type 3 | | No order restriction** | | Multiple-issue pipeline | | No order restriction** | | *If the timing template omits PA, then EX must be in order. | | **Ordered only by dependencies. |
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the AG and DF phases even if it used only registers for its operands. Dynamic pipelines allow the bypassing of one or more of the stages of the pipeline, depending on the requirements of the instruction with the specifications of the instruction. Even within the category of dynamic pipelined processors, there are at least three levels of pipeline sophistication (Table 4.5): |
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Type 1: Dynamic pipelines that require instructions to be decoded in sequence and results to be executedput away (PA)in sequence. For these types of simpler dynamic pipeline processors, the advantage over a static pipeline is relatively modest, as we shall see. In-order execution requires that the actual change of statethe storage of the data result for sequential instructionsmust occur in the order that the data were specified in the instruction sequence. Thus, for instructions with a putaway cycle, the execution may complete but the putaway must not be done until all previous instructions have put away their own respective results. All actions are conditional on the successful completion of all prior instructions. |
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Type 1-Extended: A popular extension to the Type 1 pipeline is to require decode to be in order, as well as references that affect the memory state. The execution stage of ALU operations need not be in order. In these organizations, the AG (address generate) and T (translate) stages of LD/ST instructions must be completed before any subsequent ALU instruction does a PA (putaway). The reason for this is that the translate operation may reveal that the referenced page is not now in (real) storage, and require a task swap while the page is brought in. Such a swap cannot easily proceed with an altered state subsequent to the interrupting instruction. |
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Because of these restrictions and the overall frequency of LD/ST instructions, the Type 1-Extended pipeline behaves much as the basic Type 1 pipeline. In this chapter, we treat basic Type 1 pipelines with |
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