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execution unit is the responsibility of the instruction unit. The better it is designed, the fewer the delays in the pipeline. |
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The design of the processor begins with a tentative definition of a typical instruction timing (the timing template). This also serves to give some additional information on the partitioning of the processor into stages. The execution unit consists of data paths, registers, and ALU or execution resources. The registers are defined by the instruction set to hold data values; the execution resources transform the data as specified in the instruction vocabulary. There may be multiple execution resources, perhaps one for each data type (floating point, integer, character, decimal, etc.), since it is more efficient (results in faster execution time) to execute each data type with a specialized unit. The data paths are the transmission or communication paths that connect registers with the execution units and with the memory system. |
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An instruction unit consists of the state registers as defined by the instruction setthe PSW and the instruction registerplus the instruction buffer, decoder, and an interlock unit. The instruction buffer's function is to fetch instructions into registers so that instructions can be rapidly brought into a position to be decoded. The complexity of the instruction buffer depends on the instruction set. If instructions all have a common length, the buffer may be easier to design and manage than in architectures with multiple size instructions. The decoder has the responsibility for controlling cache, ALU, registers, etc. Frequently in pipelined machines, the instruction unit sequencing is managed strictly by hardware, but the execution unit may be microprogrammed so that each instruction that enters the execution phase will have its own microinstruction associated with it. The interlock unit frequently is regarded as part of the decoder, although for purposes of our studies we separate the functions of the two. The interlock unit's responsibility is to ensure that the execution of multiple instructions has the same result as if the instructions were executed completely seriallyone after another, as in a well-mapped machine. |
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Suppose we have an R/M pipelined processor with the following instruction timimg template: |
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Ideally, instructions follow through the pipeline; one entering each cycle. |
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Each instruction takes just as long to complete as in a simple, well-mapped processor; but, ideally, the rate at which instructions are completed is one per cycle. |
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The rigid sequencing of events as just shown may or may not be required in particular pipeline processor implementations. The most restrictive form of a pipeline, sometimes called the static pipeline, requires the processor to go through all stages of the pipeline whether required by a particular instruction or not. Thus, instruction N + 1 in the preceding would go through |
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