|
|
|
|
|
|
Mainframes, Microprocessors, and the Future |
|
|
|
| |
|
|
|
|
Either consciously or unconsciously, microprocessors have followed the path of large mainframe processors, generally lagging behind the top-of-the-line mainframe computers in cycle time, features, and performance by about five to ten years. The lag has evaporated in recent years as microprocessor designers have become increasingly aggressive in the use of technology and the technology itself enables more complex functional realizations. |
|
|
|
| |
|
|
|
|
It is sometimes amusing to read in microprocessor development literature about the rediscovery of older mainframe techniques. One such concept is superpipelining, the ability of a pipelined processor to have multiple instructions in various stages of operand execution (for example, EX). Most large top-of-the-line mainframes over the past two decades have done exactly this. |
|
|
|
| |
|
|
|
|
It is still interesting to contemplate that within the next few years, microprocessors will be able to support the type of high-end processing capabilities outlined in Tables 4.2 and 4.3microprocessor ensembles supporting 10 gigabytes of storage, each with a cycle time of 6.0 nanoseconds or less,1 full vector arithmetic facilities, and perhaps 256 fiberoptic I/O channels. It is in this last area, I/O connectivity, that the mainframes have made their last stand, providing access to huge database ensembles and storage access systems. |
|
|
|
|  |
|
|
|
|
The best "mainframe" cycle time is currently 2 ns (Hitachi 3800). |
|
|
|
|
|
|
|
|
|
 |
|
|
|
|
|
|
|
|
Figure 4.2
View of a processor. |
|
|
|
|
|
|
|
|
template or execution sequence of an instruction and the allocation of cycles to functional actions that execute the instruction. Generally, the action that occurs within any functional unit requires one or more cycles. |
|
|
|
|
|
|
|
|
The general view of the processor (Figure 4.2) has a memory system, execution unit (data paths), and instruction unit. The more efficient the memory system (the larger and faster the cache, etc.), the smaller the number of cycles required for fetching instructions and data (IF and DF). The more extensive the execution unit, the smaller the number of execution cycles (EX) that an average instruction requires. The management of the cache and |
|
|
|
|
|