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| Table 4.4 Types of processors. |
| | Performance | Machine Type | Comments | | 56 CPI (typ.) | Serial or weel-mapped | See chapter 1. | | 3 CPI | Serial processor with some overlapped functions | | | 1.52 CPI | Simple pipelined processor with static pipeline | See this chapter (4). | | 1.21.5 CPI | Pipelined processors with dynamic pipeline, instruction buffering, branch prediction, etc. | See this chapter (esp. 4.44.8). | | Below 1.0 CPI | Multiple instruction issue | See chapter 7. |
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Section 4.6 treats a specialized area of pipelined processor implementation called instruction interlocks. These interlocks detect dependencies among instructions that are being processed by the pipelined processor. |
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Section 4.8 considers other miscellaneous effects in pipelined processor design and evaluation. |
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For this chapter, the pipelined processor is assumed to operate under the following constraints: |
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1. At most, one instruction is decoded each cycle. |
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2. Instructions are decoded in the sequence they appear in the program representation. |
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3. Instructions are completed in the sequence they are decoded, i.e., the original program sequence. |
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Chapter 7 removes these constraints and examines the consequences on machine performance and machine behavior and implementation. |
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4.2 Approaching Pipelined Processors |
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In this section, we look at the various stages of instruction execution used by a typical pipeline processor. As we noted in Chapter 2, all processors do not define the partitioning of instruction execution events in the same way. In one case, a designer might combine events, creating a so-called shallow pipeline consisting of just a few events or stages in the pipeline. On the other hand, a more aggressive designer might partition instruction execution into a deep pipeline consisting of many stages of instruction execution. In this section, we look at various possibilitiesways that have been used to partition instruction execution into pipelineable events. |
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In the design of a pipelined processor, a processor framework is neededa picture of the functional units that compose the processorso that tradeoffs can be made among these functional units to provide an overall optimum cost-performance design. Before beginning, we must know the timing |
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