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Similar evolution of product lines can be seen in the Intel 80X86 family of microprocessors, or the Motorola 680X0 family. |
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Two key elements in the design of a processor are the definition of processor performance and some notion of what type of work is to be performed. The design and performance evaluation process involves two interlocking hierarchical models: a model of the design and a model of the workload. |
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Analysis is usually based on an instruction-level workload model. This requires instruction distribution data describing the operational characteristics of a machine when it is executing a program. If a manufacturer is concerned with a product that uses the same architecture as previous machines, like IBM with the S/390 architecture, we ought to be able to obtain data that characterizes the nature of programs when they are in execution. How do branches behave? How do the decimal operations behave? How do the string operations behave? What is the average length of an instruction? What is the frequency of use of various instruction formats? A stable architecture provides a significant advantage, providing behavioral available data that allows well-informed design decisions. A new architecture requires more guesswork unless it has certain similarities to the architectures that have preceded it. The only possibility is to use or extrapolate from data obtained from another product. Many early microprocessor designs were predicated on PDP-11 and S/370 data. Cache models were based on models of existing machines and then extrapolated to proposed microprocessor designs. |
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4.1.3 Organization of the Chapter |
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In Chapter 1, we saw serial machines that execute with little or no overlap of actions. While serial machines include many well-known older machines (Intel 80286, VAX 780, etc.) and thus may have historic interest, there is no current design in such machines (Table 4.4). Today's designs are usually of the pipelined processor type with an assortment of functional improvements to improve performance. The performance limit of these machines is one cycle per instruction (CPI) although, as we shall see, this is not realizable in practice. This chapter covers processor design and evolution techniques that correspond to the general microprocessor state of the art (Table 4.4). Chapter 7 discusses more advanced approaches. |
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To begin our discussion, we look at types of pipelined processors (section 4.2), observing how the pipeline can be represented and the timing variability of various pipelined processor implementations. |
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The next section (4.3) develops a methodology for evaluating the performance of a pipelined processor given certain instruction timings and the frequency of occurrence of certain pipeline disruptions. |
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Section 4.4 looks at implementation issues for pipeline processors: the number and extent of buffers required in certain areas of the processor, methods of improving the flow of instructions to the decoder to minimize pipeline disruptions, and other issues. |
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