< previous page page_146 next page >

Page 146
Table 3.2 Instruction size distribution by program category.
2-byte Reg-Reg Avg.%
4-byte Mem-Reg Avg.%
6-byte Mem-Mem Avg.%
Composite Average
Design Target: L/S
0%
100%
0%
4B
Design Target: R/M
Sci./Sys. Environments
40%
60%
3.2B
Commercial Environment
30%
50%
20%
3.8B
Design Target: R+M*
Sci./Sys. Environments
25%
50%
25%
4B
Commercial Environment
30%
50%
20%
3.8B
* In current practice, R+M instruction sizes are byte-variable. The data presented here simply approximate the expected distribution. Thus, the entry "2 bytes" represents instruction sizes of 1 and 2 bytes; "4 bytes" represents instruction sizes 3 through 5 bytes; and "6 bytes'' represents instruction sizes of 6 bytes and longer.

Table 3.3 Expected instructions executed per 100 HLL operations (scientific application).
Architecture
Instructions per 100 HLL Operations
L/S
200
R/M
180
R+M
120

Table 3.4 Expected Gibson classification profile for scientific applications by architecture. Expected instructions executed per 100 HLL operations. (For a breakdown of operations within a class, see indicated table.)
Scientific
L/S
R/M
R+M
See Table
Move (integer, floating point)
107
(54%)
87
(48%)
27
(23%)
3.15
Branch
26
(13%)
26
(15%)
26
(22%)
3.10
Floating Point
24
(12%)
24
(13%)
24
(20%)
3.14
Fixed Point
16
(8%)
16
(9%)
16
(13%)
3.14
Shift, Compare, Logical (word)
27
(13%)
27
(15%)
27
(22%)
200
180
120

 
< previous page page_146 next page >