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| Table 3.1 Evolution of the MIPS instruction set. |
| | Originarl MIPS R2000/R2010 Instruction Opcodes | | Load/Store: | LB, LBU, LH, LHU, LUI, LW, LWCz, LWL, LWR, SB, SH, SW, SWCz, SWL, SWR | | Computational: | ADD, ADDI, ADDIU, ADDU, AND, ANDI, DIV, DIVU, MULT, MULTU, NOR, OR, ORI, SLL, SLLV, SLT, SLTI, SLTIU, SLTU, SRA, SRAV, SRL, SRLV, SUB, SUBU, XOR, XORI MFHI, MFLO, MTHI, MTLO | | Jump and Branch: | BCzF, BCzT, BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE, J, JAL, JALR, JR, RFE, | | Coprocessor: | CFCz, COPz, CTCz, MFCz, MTCz | | Special: | BREAK, SYSCALL TLBP, TLBR, TLBWI, TLBWR | | Floating-point: | ABS, ADD, C, CVT, DIV, MOV, MUL, NEG, SUB | | MIPS R4000 Extensions | | Branch likely: | BCzFL, BCzTL, BEQL, BGEZL, BGEZALL, BGTZL, BLEZL, BLTZL, BLTZALL, BNEL | | Load/Store doubleword: | LDCz, SDCz | | Floating-point: | ROUND, TRUNC, CEIL, FLOOR, SQRT | | Conditional trap: | TEQ, TEQI, TGE, TGEI, TGEIU, TGEU, TLT, TLTI, TLTIU, TLTU, TNE, TNEI | | Special: | CACHE, LL, SC, SYNC, ERET |
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Comments: The R2000 and the R3000 [153] have the same instruction sets and the same basic architecture. The R4000 [154] was enhanced to include a floating-point unit and instruction and data caches on board. Also, the pipeline in the R4000 was increased from 5 stages to 8, to improve the clock rate. |
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The onchip caches are direct-mapped and virtually indexed. The data cache is write-back. New instructions were added to deal with these changes and to allow multiprocessor configurations: |
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1. Due to the longer pipeline, "branch likely" instructions were added to reduce the branch penalty using statically predicted branches. |
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2. Load and store double word were added to coprocessor instructions to boost their floating performance. The R4000 has the floating point onchip, but it still uses the coprocessor instructions. |
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3. Floating point was enhanced to do square root. |
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4. Cache control instructions were added so that cache lines could be invalidated or flushed under software control. |
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5. Conditional trap instructions were added. |
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6. Multiprocessor synchronization instructions (Load linked, Store conditional, and Sync) were added. |
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