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Function units B, D, and E can be subdivided into two equal delay stages. If the expected occurrence of pipeline breaks is b = 0.25 and clocking overhead is 2ns (k =O): |
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(a) Ignoring quantization, what is the optimum number of pipeline segments (round down to integer value)? |
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(b) What cycle time (with quantization) does this give? |
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(c) Compute the pipeline performance with this cycle time. |
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(d) Can you find a better cycle time? |
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(e) If there is an additional±1 ns uncontrolled clock skew in (b), what is the adjusted cycle time? |
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10. Compute the area in rbewith and without aspect-mismatch adjustment of a 32KB direct-mapped cache with 256-bit lines and a 20-bit tag. |
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11. A processor die (1.4 cm ´ 1.4 cm) will be produced for five years. Over this period, defect densities are expected to drop linearly from 1.5 defects/cm2to 0.8 defects/cm2. The cost of 6-inch wafer production will fall linearly from $5,000 to $3,500, and the cost of 8-inch wafer production will fall linearly from $10,000 to $6,500. Assume production of good devices is constant in each year. Which production process should be chosen? |
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12. DRAM chip design is a specialized art where extensive optimizations are made to reduce cell size and data storage overhead. For a cell size of 135l2, find the capacity of a DRAM chip. Process parameters are: yield =10%, rD = 1 defect/cm2, feature size = 1moverhead consists of 10% for drivers and sense amps. Overhead for pads, drivers, guard ring, etc., is 20%. There are no busses or latches. |
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Since memory must be sized as an even power of 2, find the capacity and actual gross area (eliminating wasted space) and find the corresponding yield. |
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13. Compute the cost of a 1M´ 1b die, using the assumptions of (12). Assume a 21 cm diameter wafer costs $5,000. |
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14. Suppose a 2.3 cm2 die can be fabricated on a 15cm wafer at a cost of $5,000, or on a 20 cm wafer at a cost of $8,000. Compare the effective cost per die for defect densities of 0.5 defects/cm2 and 1 defect/cm2. |
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15. The net area required for a processor is 280mm2. The processor can be implemented using one, two, four, or eight chips. Assume that the design is partitioned equally among all chips. Model the cost per chip as $50 per good device for packaging and testing plus the effective cost of the die. Devices are produced with 15-cm wafers costing $4,000, and the defect rate is 1 defect/cm2. Assume that a defect anywhere on the die renders the device inoperable. Tabulate the cost of the processor for each of the four possible partitions. The area overhead for pads, etc., is 20% on each chip. |
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