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16. In Cragon [61], several architectures are compared, including: |
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3M three address memory to memory; |
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| OP | A | B | C | | 2M two address memory to memory; | OP | A | B | | | ACC single accumulator; | OP | A | | | R/M register set (16 registers);
(R plus RB, base register, occupies one byte) | OP | R | RB | A | | S stack | OP | or | OP | A |
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Assume one byte is allowed for opcode and from one to three bytes are allocated for an address. |
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Plot the expected static code size for each architecture relative to S (stack) for address sizes of one, two, and three bytes. (Compute the size of a functional instruction, then add the size of the fraction of overhead instructions denned by the M-ratio.) Assume: |
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No procedural instructions. |
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M-ratio of zero for 3M. |
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M-ratio of 0.1 for 2M. |
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M-ratio of R/M is 2.0. |
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M-ratio for stack is the same as ACC, 2.5. |
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17. Continue Cragon's analysis of problem 16. Plot the expected execution time for each architecture relative to stack for 2-, 3-, and 5-cycle memory access with a three-byte address only. Each memory access fetches a single instruction or data operand regardless of size. Assume a well-mapped host with one cycle for Decode (D), one cycle for Address Generate (AG), and one cycle for Execute (EX). Note that no EX cycles are required with M-type instructions. |
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18. For each machine model defined in problem 17, find the CFA measures (Section 2.6.2) of M and R. Be sure to include the effects of referencing IC, IIR, and SR registers (each 32 bits). |
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19. For a routine (procedure) to find the roots of the quadratic equation (assume a square root instruction), find the HLL measures of: |
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(a) Instruction count. |
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(b) Memory reads and writes. |
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Assume the three arguments are in memory and the results must also be written to memory. |
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