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		(a) What is the cycle time that maximizes performance without allocating multiple cycles to a segment?



		(b) What is the total time to execute the function (through all stages)?



		(c) What is the cycle time that maximizes performance if each segment can be partitioned into sub-segments?



		2. Repeat problem 1 if there is a 1 ns clock skew (uncertainty of ±1 ns) in the arrival of each clock pulse.



		3. A four-segment pipeline to execute a function has the following parameters:

Segment #	P_max	P_min
1	14	7ns
2	12	9ns
3	16	10ns
4	11	5ns



		The clock overhead, C, for each register stage is 3ns.



		(a) If no controlled clock skew is allowed, what is the latency of execution (through all stages) for the function? What is the minimum cycle time?



		(b) If we now allow controlled clock skew to take advantage of P_min what is the latency, minimum cycle time, and clock skew required at each stage?



		4. Repeat problem 3 if there is an additional 1 ns of uncertainty in the arrival of the clock at each segment.



		5. Plot S_optwith respect to clock skew factor (k) for k = 0.05 to k = 0.20. Assume T = 120ns, C = 5ns, and b = 0.2.



		6. We can generalize the equation for S_{opt/sub> by allowing for pipeline interruption delay of S -a cycles (rather than S - 1), where S >a}_{³ 1. Find the new expression for Sopt}.



		7. (a) Show that the effect of uncontrolled clock skew(±d) in a regular pipeline is to increase C, and hence cycle time, by 2d.



		(b) Show that the effect of uncontrolled clock skew (±d) in a wave pipeline is to increase C, and hence cycle time, by 4d.



		8. Repeat Study 2.1, with the delay in R®ALU®R = 16 ns and instruction and data cache data access = 8ns.



		9. Acertain pipeline has the following functions and functional unit delays (without clocking overhead):

Function

Delay

A

6

B

8

C

3

D

7

E

9

F

5

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