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Page 136
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P. Kogge. The Architecture of Pipelined Computers. McGraw-Hill, New York, 1981.
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S. Kunkel and J. Smith. Optimal pipelining in supercomputers. Proc. 13th Annual Symposium on Computer Architecture, pages 404411, 1986.
Area Modeling
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D. Marple and A. El Gamal. Area-delay optimization of programmable logic arrays. Proc. 4th MIT Conference on Advanced Research in VLSI, pages 171194, April 1986.
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C. Mead and L. Conway. Introduction to VLSI Systems (Series in Computer Science). Addison-Wesley, 1980.
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J. Mulder, N. Quach, and M. Flynn. An area model for on-chip memories and its application. Journal of Solid State Circuits, 26(2), February 1991.
Economics of Processor Development
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J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Mateo, CA, 1990.
Instruction Set Optimization
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S. Fuller and W. Burr. Measurement and evaluation of alternative computer architectures. Computer, 10(10):2435, October 1977.
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A. Tanenbaum. Structured Computer Organization (Series in Automatic Computation). Prentice-Hall, Englewood Cliffs, NJ, 1976.
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J. Huck and M. Flynn. Analyzing Computer Architectures. IEEE Computer Society Press, New York, 1989 (2nd edition).
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W. Stallings. Reduced Instruction Set Computers. Tutorial. IEEE Computer Society Press, Los Alamitos, CA, 1990.
2.11 Problem Set
1. A four-segment pipeline implements a function and has the following delays for each segment (b = 0.2):
Segment #Maximum delay*
117 ns
215 ns
319 ns
414 ns
*Excludes fixed clock overhead of 2 ns (k = 0).

 
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