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there has been a good deal of interest in alternative approaches to clocking, such as asynchronous clockingthe use of logic with completion signals to allow the entry of new data. Early work at the University of Illinois under Muller and Bartky [208, 209] basically outlined how such a logical schema would work. General considerations are outlined in Ungar [293] and Miller [197]. |
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For a general discussion on clocking schemes for high-speed systems, [294] and [297] are particularly useful. Our treatment of some of the aspects of partitioning of time and cycle time determination follows the work of Dubey [77] and Kunkel and Smith [175], using some of the formulations of Hallin [118]. |
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Work on very fast cycle times that employ storage in the form of guaranteed minimum delay was first published in [18]. Although the discussion there is limited, it was generalized by [60]. Recent attention to the so-called wave pipelining method generally references the work of Wong [310, 311] and Klass [164]. |
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Optimum use of area is a standard concern in microprocessor design and is treated in various ways by works in that subfield. The earliest comprehensive reference is Mead and Conway [194]. Area optimization is generally focused on particular functions such as in the work of Marple and El Gamal [190]. |
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Area optimization with respect to cache function is discussed in Chapter 5. Also, see Flynn et al. [94] for a more complete discussion of I-cache instruction code density issues. The general area model we follow was initially developed by Mulder [206, 207]; see also the work of Mudge and his colleagues [214, 295] which uses the rbe model for processor tradeoffs. |
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There is an enormous body of literature on instruction sets, but significantly less on instruction set evaluation. A good deal of interesting data is presented in several works [156, 277, 52, 304, 127]. Our data presented in this chapter and in the next is based upon the work of Huck [135, 136], as it both normalized compilers and did a comparative analysis on instruction sets. |
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For discussion of the instruction set measures as a basis of high-level language defined measures of program and machine behavior, see Flynn and Hoevel [93]. There have been numerous machine-specific studies of either individual instruction sets or comparative treatments of several instruction sets; particularly noteworthy is the work of Clark [52], Wiecek [304], Lunde [187], and Huck [135]. The analysis of code density or the marginal utility of code density register windows is taken from Flynn et al. [94]. |
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Basic Issues in Clocking and Pipelining |
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S. Ungar. Asynchronous Sequential Switching Circuits. Interscience. Wiley, New York, 1969. |
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K. Wagner. A survey of clock distribution techniques on high speed computer systems. Technical Note CSL-TN-86-309, Stanford University, December 1986. |
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