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a comprehensive analytic basis for instruction set design is not at hand. A lack of area models mentioned earlier inhibits a good deal of sensible instruction set tradeoff, but comprehensive well-correlated instruction set analysis (accounting for compiler, systems, I/O, etc., effects) remains a precious commodity. |
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Data Note 1 (Tables 2.6-2.9). |
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The data in these tables are taken from Huck [135]. They are based on a study of five scientific programs. Compiler effects were carefully normalized so as to be comparable to other studies. The notion of an HLL operation is more completely defined in Huck where it is referred to as a canonic measure or CI measure. |
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Reliability. The data seem generally consistent with other published results where compiler effects have been similarly normalized. |
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Stability.Dynamic instruction count should be relatively stable as a fraction of the HLL operation count. The instruction count, however, is a strong function of compiler optimization. Similarly, memory object read-writes (Table 2.9) are a direct function of the type of source program used, and a strong function of the register allocator available in producing the final object code. |
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Data Note 2 (Figures 2.51 and 2.54). |
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The data presented here are from Alpert [13] and Mulder [206], based upon a series of medium-sized Pascal benchmarks generally characterized as representing a workstation environment. |
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Reliability. While the general trends and conclusions ought to be unaffected by most problem environments, different applications and source languages will display different overall behavior. Data traffic is generally not a function of architecture, but simply a function of the number of registers available for allocation and the type of register allocator used. The relative results are expected to be reliable. |
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Stability. The reduction of relative data traffic with a relatively small number of registers seems to be a stable result. The actual achieved relative data traffic is, however, quite dependent on the program studied. One should expect significant variations in the actual achieved relative data traffic as a function of application. |
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2.10 Annotated Bibliography |
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The determination of cycle time in modern processors is closely associated with the design of synchronous, hazard-free logic implementations. Much of the basic work on hazard-free sequential circuits was done in the 1950s and 1960s. (See, for example, E. J. McCluskey, Introduction to the Theory of Switching Circuits, McGraw-Hill, New York, 1965.) Since the late 1950s |
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