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Page 131 Figure 2.53 The processor register: D-cache model. Figure 2.54 Execution time for register windows or multiple register sets (MRS) compared with a single (16-entry) register set (SRS) plus a data cache, each occupying area measured in dual ported register word (32b) equivalents. Data cycle ratio is defined as the execution time for an ideal pipelined processor (SRS) with cache or with MRS compared to the same processor with zero cache (misses each reference). We can use another simple D-cache model to evaluate the value of register windows, organized as (8,8,n). Consider Figure 2.53. We assume that the processor may read two registers and write one register within a cycle. The D-cache access requires one cycle. Memory access (from either registers or D-cache) is three cycles, and a total of seven cycles is required to process a cache miss. Suppose again that we use the area model to evaluate the advantages of register windows compared to a single register set plus cache occupying the same area. Register windows clearly perform a valuable function by reducing the cost of procedure call and return; but suppose we took a single register set (SRS) of 16 registers and added a data cache occupying the same area as a register window (MRS) implementation. Again calling on our rbe model, and assuming a three-cycle memory access time, we can compare the area effectiveness of the two approaches, as in Figure 2.54. We assume that both architectures are L/S, with the area in addition to the base processor allocated either to register windows or to a single register set with data cache. Register windows improve performance on call and return, but caches are able to capture localities containing dynamically allocated data structures that cannot be assigned to registers. Thus, over the long run, caches appear to be a more effective use of area, although for certain values of area there is little to distinguish one approach from the other.
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