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1. For a three-cycle memory, a single register set of about 16 registers plus a data cache seems to be more area-effective than multiple register windows. |
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2. As the memory access time increases beyond three cycles, data indicate that the single register set approach plus the data cache is even more effective than the register window approach. |
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3. Since register windows require a significant amount of chip area and increased control complexity compared to the single register set plus cache approach, MRS (windows) may cause a deterioration in the cycle time due to increased register select logic. |
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4. If a significant amount of area is available for data cache and a data cache is added to an MRS implementation, then ultimately this combination will use fewer cycles than a single register set implementation with data cache using the same area. The MRS approach saves additional time at procedure call. |
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Basic Optimization Design Rules: |
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1. Within instruction set (compatibility, etc.) constraints, determine effect of instruction set enhancements on code density and I-cache size and decoder area. For purposes of this optimization assume separate I- and D-caches split about evenly. |
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2. Within constraints outlined in (1), determine the effects of register set enhancements on memory traffic and memory access delay. Optimize D-cache/register area allocation. |
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3. Based on any changes made in (1) and (2), reevaluate cycle time and any adverse effect on performance. |
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Cycle time is of paramount importance in microprocessor design. It is largely determined by technology, but is significantly influenced by secondary considerations such as clocking philosophy and pipeline segmentation. |
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Once cycle time has been determined, the designer's next challenge is to optimize the cost-performance of a design by making maximum use of chip areausing chip area to the best possible advantage of performance. A technology-independent measure of area called the register bit equivalentthe rbeprovides the basis for storage hierarchy tradeoffs among a number of important architectural considerations. |
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The instruction set is the glue that brings together implementation and technology and forms the specification of the ''user-visible logical machine." |
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The dynamic character of the high-level language source program is represented by HLL measures of the program. The number of HLL instructions |
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