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Figure 2.42
Relative I-cache traffic for three different code densities. |
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| Load/Store | 1.0 | | Register/Memory | 0.8 | | Register+Memory | 0.6 |
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Using our cache area model, suppose the same area was available for I-cache to each of our three processor types. Figure 2.42 shows the relative I-cache traffic for our three different levels of code density corresponding to our three different architectures. Each architecture reduces its cache traffic (on-chip cache to memory) and improves its performance by having an I-cachefor this simple model, the larger the better, but across a reasonable amount of I-cache areaup to 10,000 rbethe more densely encoded architectures continue to improve their relative cache advantage over the less densely encoded architectures. Of course, this data does not tell the whole story, since there are several other important considerations: |
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1. The more dense architectures require more instruction decoder area, so it is unfair to simply allocate the same amount of I-cache area to each of these three processors. |
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2. The relative effect on performance of the I-cache diminishes as the cache gets larger. |
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3. Large decoders may limit the cycle time of the processor, distorting the comparisons. |
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Suppose we now compare the marginal utility of extending the load/store architecture by either adding an I-cache or recoding the instruction set to either register/memory or register + memory and then adding an I-cache. An estimate of the additional area cost to go from a load/store machine to a register/memory machine is about 250 rbe [94]. This includes an additional 32-bit register and multiplexers for justifying 16-bit half-word instructions so that they may be properly decoded. A very rough estimate of the register+memory decoder area would be approximately 4,000 rbe (approximately 500 register byte equivalents) in decoder overhead to accommodate the additional formats and instruction sizes. Assuming a cache access time |
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