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Instruction Set Hype (continued) |
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Formally defining instruction sets, especially in mainframe design, without strongly considering implementation considerations might not be a fatal error. After all, an ill-considered additional functional unit might require an additional several chips out of twenty or more in an implementation. In microprocessor design things are much different. Processors must fit on a single chip. If the functionality is overblown with respect to the chip area, implementations can be disastrously slow in executing the required instructions and functions. |
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RISC technology is the result of a realization in the early 1980s that chip area was quite limited and that efficient instruction execution could be achieved with minimum functionality instruction sets (operand vocabulary, formats, etc.). |
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Over time, RISC implementations have added features and functions. The IBM RS/6000 introduced a fused multiply and add instruction. RISC processor implementations have now almost universally adopted the IEEE standard, probably the most complex floating-point representation ever proposed. As most designers readily recognize, there is nothing "reduced" about it. |
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Implementation capacity changes rapidly; instruction sets change more slowly. The instruction set designer not only must recognize today's technology limitations, but also must be able to intelligently predict the evolution of future technology. Over the longer term, there is no single answer to instruction sets, just as there is no single fixed implementation technology. |
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Figure 2.41
The processor register: I-cache model. The
processor accesses cache in one cycle. The
cache requires n cycle. The cache requires n cycles to access
memory on a miss (n > 1). |
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