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Figure 1.10
The R/M architecture.
R/M format: one source
operand may lie in
memory, the other
source operand must be
a register that also
serves as the destination
(a two-address format,
sometimes called one
and one-half address
because of the
preceding limitation).
Character-based
operations are an
exceptional case. Their
format is Mem OP Mem
® Mem. |
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For our R/M architecture, the result of a simple (e.g., integer or floating-point) ALU operation must go to the register that was used as an operand source (Figure 1.10). The R/M architectures generally trace their evolution to the IBM System 360 introduced in 1963 (later System 370, the 3XXX models, Enterprise system, and S/390); there have been many variations on this basic architecture style. Most general-purpose modern mainframe computers follow the R/M style (IBM, Amdahl, Hitachi, Fujitsu, etc., which all use the IBM instruction set), as well as several microprocessor architectures (Intel x86 series). There are many variant architectures included within the R/M designation. We use data from IBM mainframe environments as representative of the R/M architecture. The applicability of this data to Intel-type machines is very approximate, since Intel uses byte-variable instructions, has selected instructions with memory destinations, and uses special implied registers. Our R/M architecture anticipates some variability in instruction size: we assume that the register-to-register operations are 16 bits, while the register-to-memory operations are 32 bits. |
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R+M or Register-plus-Memory architectures allow formats to include operands that are either in memory or in registers. Thus, for example, an ADD may have all of its operands in registers or all of its operands in memory, or any combination thereof. The R+M architecture generalizes the formats of R/M (Figure 1.11). The outstanding example of the R+M architecture is Digital Equipment's VAX series of machines. VAX is an extension of the older PDP-11 introduced in the late 1960s and generalizes the use of the register set through the use of register modes, which are described later. The use of an extended set of formats and register modes allows a powerful and varied specification of operands and operation type within a single instruction. Microprocessors such as the Motorola M680x0 series or the ATT WE 32100 also belong to the R+M architecture class, although they do not have instruction set capability as extensive as VAX. Unfortunately, format and mode variability complicates the decoding process so that the |
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