|
|
|
|
|
|
|
Figure 1.11
The R+M architecture. R+M
format: operands may lie in
either register or memory.
Three operands are
independently specified
(three-address) and each
may specify either register
or memory. Formats also
include the two-address
type where one source
operand address (register
or memory) is the same as
the destination. |
|
|
|
|
|
|
|
|
process of interpretation of generalized instructions can be slow (but R+M architectures make excellent use of memory/bus bandwidth). |
|
|
|
|
|
|
|
|
The L/S type of processor architecture uses fixed-size instructions (typically 32 bits) with uniform field interpretation (size typically 32 bits) and with a regular execution sequence. At the other extreme, the R+M architecture frequently uses compact and flexible representation of program actions. Instruction flexibility as represented by the R+M architecture provides a more compact representationfewer bits to fetch instructions for execution, fewer numbers of instructions to executewhile the more restrictive L/S architecture provides a more rapid execution of each instruction, but executes more instructions. Because of its emphasis on pipelined processors, this text stresses the L/S architectures and R/M architectures, as they are the most natural candidates for pipeline implementations. Current R+M architectures are more difficult to realize in pipeline implementations because of their extensive use of variable operand specifiers (the operand modes). While it would be possible to create more regular implementations of R+M architectures, perhaps equally suited for pipelining, these are not yet common in the marketplace. |
|
|
|
|
|
|
|
|
One of the most important aspects of an architecture is the format (size, shape, and structure) of the data values that are operated on by the instruction set. The data type defines the format and use of data objects and implies the operations that are valid for each type. For most familiar machines, the different data types can be broken down into the following classes (Figure 1.12): |
|
|
|
|
|
