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Figure 1.9
The L/S architecture.
L/S format: all
operands for ALU
operations must lie in
registers. |
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croprocessors integrate floating-point hardware and registers on the processor chip. |
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Our generic approaches assume a program status word, which consists of various types of control status information, including condition codes (described later) set by the instruction. With this common core, the three instruction set types are: |
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1. The L/S, or Load-Store architecture. |
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2. The R/M, or Register-Memory architecture. |
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3. The R+M, or Register-plus-Memory architecture. |
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Figure 1.8 relates these instruction set types to common machines provided by the better known manufacturers. |
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The L/S architecture describes many of the RISC (reduced instruction set computer) microprocessors (IBM RS/6000, MIPS R-series, Hewlett-Packard's PA-RISC, Sun Microsystem SPARC, Motorola M88000). All values must be loaded into registers before an execution can take place. An ALU ADD instruction must have both operands and result specified as registers (three addresses). Thus, an ADD with one operand in memory is not allowed (Figure 1.9). The purpose of the RISC architecture is to establish regularity of execution and ease of decoding in an effort to improve overall performance. RISC architects have tried to reduce the amount of complexity in the instruction set itself and regularize the instruction format so as to simplify decoding of the instruction. A simpler instruction set with straightforward timing is more readily implemented. |
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The R/M or Register-Memory architectures include instructions that can operate both on registers and with one of the operands residing in memory. Thus, for the R/M architecture, an ADD instruction creates the sum of a register value and a value contained in memory, putting the result into the same register (two addresses), This use of a memory value is not allowed in the L/S architecture (Figure 1.10). |
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