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Figure 2.38
I-stream tradeoff: increasing the
instruction encoding increases the
I-decoder size (area), but decreases
the I-cache size (area). |
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Figure 2.39
D-stream tradeoff: similarly,
increasing the register set size
decreases the D-cache size. |
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The Instruction Stream Increasing the number of formats reduces the number of instructions executed. Increasing the degree of encoding of an instruction set reduces the average size of an instruction. Decreasing the number of instructions executed and the size of the average instruction decreases the number of memory accesses required to execute a particular program (Figure 2.38). These factors improve program execution. On the other hand, such improvements increase the size of the instruction decoder (they require more area, which may increase the cycle time) and require more sophisticated compilers. Moreover, multiple instruction sizes and multiple instruction formats create difficulty in managing the overlapping or pipelined execution of instructions. This extra decode area, for example, must be traded off against the extra instruction cache size that results from a poorly encoded instruction set. The designer must find an optimum balance for the application environment. |
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The Data Stream A large register set reduces the read and write requests to memory, but adding registers has a limited usefulness beyond a certain pointas we shall see later, each additional register is less valuable than a register in the initial complement of registers. Moreover, in a user environment with frequent interrupts (such as realtime or multitasking applications) that result in the saving and restoring of these registers, these additional registers can become a burden. There is a tradeoff between enlarging the register set size and using the area for other items such as a small data cache. A large register set size decreases read and write traffic to memory (Figure 2.39). However, a small register size with a data cache occupying the equivalent amount of area may provide better overall performance. |
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Cycle Time Considerations Many things affect cycle time, which is determined by the longest path through the processor logic. The longest delay path varies from implementation to implementation, but it is usually found in one of the following areas: |
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