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Page xiii 10.1.2 Design Alternatives 665 10.1.3 Pipeline Timing Analysis 665 10.1.4 Pipeline Penalty Analysis 671 10.1.5 Cache and Memory Analysis 676 10.1.6 Cost-Performance Analysis 677 10.2 Area Performance Analysis of Processors 683 10.2.1 The Problem 683 10.2.2 Specifications 685 10.2.3 Assumptions 688 10.2.4 The Design 688 10.2.5 Analysis 704 10.3 Study Results 717 10.4 Conclusions 718 Appendix A DTMR Cache Miss Rates 719 A.1 Basic DTMR 719 A.2 Associativity Adjustments 719 A.3 User + System 721 A.4 Transaction-Based Systems 722 A.5 Multiprogrammed (Warm Cache) Environment 728 Appendix B SPECmark vs. DTMR Cache Performance 741 Appendix C Modeling System Effects in Caches 743 C.1 Cold Start Cache 743 C.2 Cache Misses in Multiprogramming Environment 744 Appendix D New DRAM Technologies 747 D.1 Typical Performance Enhancements 747 D.2 Enhanced DRAM 748 D.3 Synchronous DRAM 748 D.4 Cache DRAM 748 D.5 Rambus DRAM 748 D.6 Ramlink DRAM 749 D.7 Chip Level Summary 749 Appendix E M/G/1 Queues 751 Appendix F Some Details on Bus-Based Protocols 755 Bibliography 765 Index 782
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