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Figure 2.27
A baseline die floorplan. |
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Summary of Area Design Rules: |
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1. Compute target chip size from target yield and defect density. |
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2. Compute die cost and determine whether satisfactory. |
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3. Compute net available area. Allow 20% (or other appropriate factor) for pins, guard ring, power supplies, etc. |
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4. Determine the rbe size from the minimum feature size. Then determine register set size and ALU. |
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5. Continue allocating area until the core processor size is determined. |
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6. Subtract core processor size (5) from net available area (3). This is the die area available for processor optimization. |
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2.4 Technology State of the Art |
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Tables 2.3 and 2.4 illustrate some of the current technology parameters for a few representative workstations and mainframes. |
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There is a general misconception that mainframe processors are "big" while workstation processors are "small." The processor (only) in a typical mainframe uses about 40100 chips and occupies less than 1/2 ft3. Mainframes are usually configured with 48 processors, vector facilities, large memory, and extensive I/O, usually packaged in a large frame. |
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The workstation processor usually fits a single die, but requires a large number of support chips for memory and I/O. A big difference between workstations and mainframes is in the cooling and power requirements. Workstations are air-cooled with modest power supply requirements. Mainframes |
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