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which occupies an area of: |
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| FP register file | | | FP adder | | | FP multiplier = 1.5 adder | | | Support for divide | | | Subtotal FP | | | *Includes register bypass support, as discussed in Chapter4. |
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The subtotal for the floating-point hardware then is 37.8A, or 37.8mm2. |
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Latches, Buses, and (Inter-unit) Control For each of the functional units, there is a certain amount of overhead to accommodate nonspecific storage (latches), inter unit communications (buses), and interunit control. This is allocated as 10% for overhead for latches and 40% overhead for buses, clocking, and overall control. These overhead factors in microprocessor floor planning correspond to actual residential floor planning. They are analogous to the allowances for corridors (communications buses) and for closets (storagelatches). |
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Latches (10% of FP and integer) |
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Bus and control (40% of FP and integer) |
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Total Processor Area We can now summarize the area required for the processor as follows: |
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| Integer processor (net) | | | Floating-point hardware (net) | | | Latches and buses | | | Processor area | |
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Cache Area Out of our net area of 184mm2, the processor occupies an area of 80.9mm2. This leaves 103.1mm2 available for cache. However, bits and pieces that may be unoccupied on the chip are not always useful to the cache designer. These pieces must be collected into a reasonably compact area that accommodates efficient cache designs. |
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For example, where the available area has a large height-to-width (aspect) ratio, it may be significantly less useful than a more compact or square area. In general, at this early stage of microprocessor floor planning, we allocate another 10% overhead to aspect ratio mismatch. This leaves a net available area for cache of 92.8 mm2. |
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From our earlier discussion, we see that 1,481 rbe can be accommodated in 1 mm2. This means that approximately 137,437 rbe is available for the cache (1481 ´ 92.8). Since each cache bit only occupies 0.6 rbe, we have about 229,000 bits or 28.6 Kbytes available for cache. Out of this must come both the data array and the cache directory (Figure 2.27). |
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